1. Field of the Invention
The present invention relates to memory devices such as dynamic random access memory (DRAM) and static random access memory (SRAM) devices and to an associated power-saving writing method.
2. Description of the Related Art
Due to high demands of portable devices, power consumption has become a major concern in chip design, especially in embedded memories like dynamic random access memory (DRAM) and static random access memory (SRAM). Memory can cover around 70% to 90% of the total chip area of a device and, hence, can contribute significantly to the power consumption of the chip or chips of the device.
A high power consumption of a chip can have severe impacts on the routing lines of a chip. Due to the ohmic resistance of the routing lines, heat can be created, which may entail a necessity to provide a heat sink for removing heat. Moreover, a high power consumption of a chip can entail a relatively large electrical current density in the routing lines, which may increase the likelihood of electromigration effects and other degradation processes occurring. Such degradation processes can reduce the lifetime and robustness of a chip. Moreover, a high power consumption of a chip can reduce the lifetime of a battery supplying electric power to a device. Furthermore, a high power consumption of chips can increase the likelihood of electromagnetic interference (EMI) occurring, which can adversely affect the security of devices such as smart cards.
There are techniques for improving the performance of memory devices, which include the use of dual wordline architecture, and the use of bank type architecture. Dual wordline architecture allows reducing bitline precharge power, while entailing a relatively low area penalty. The dual wordline technique can reduce the bitline precharge power by half, thus saving about 25 to 30% of the memory cut power. Bank type architecture has less impact on power consumption, but can increase operating speed, while having a high area impact. Bank type architecture has been found to be less preferable for low area and low power applications such as smart cards and automotive electronics.
U.S. Pat. No. 5,784,320 discloses a write control unit, coupled to a memory cell, for controlling write operations to the memory cell. The write control unit includes a write qualification unit that qualifies the write operation. The write qualification unit includes a first input for receiving a first data signal that includes a current data value of the memory cell. The write qualification unit also includes a second input for receiving a second data signal that indicates a data value to be written to the memory cell. The write qualification unit enables a write operation to the memory cell only if the first data signal is different from the second data signal (i.e., the current data value and the data value to be written are different). If the first data value and the second data value are the same, the write qualification unit suppresses the write operation.
Since write operations are performed only if the data to be written into the memory cell differs from the current data value of the memory cell, the write control unit of U.S. Pat. No. 5,784,320 allows to reduce the write power, in particular if the memory device is operated at a relatively high voltage where a full voltage swing of bitlines performed for writing data to the memory cell requires more power than reading data from the memory cell. However, the write control unit of U.S. Pat. No. 5,784,320 is less efficient if the memory device is operated at low voltage, as can be done in current memory devices specifically designed for low power operation. Moreover, the write circuit of U.S. Pat. No. 5,784,320 requires extra circuit area, and the time required for writing data to the memory device can be almost doubled, since a read operation requiring extra time is performed before data is written to the memory device.
U.S. Pat. No. 6,934,213 discloses a method and a circuit for reducing power consumption during write operations in a RAM. In a RAM comprised of a plurality of memory cells, the bit lines that are coupled to each memory cell in the RAM and used to read and write data into the cell are coupled through charge share control circuitry to a charge sharing line. During write operations, the bit line that will receive a zero value is coupled to the charge share line before data is written to the cell. The charge share line equalizes the charge on the selected bit line and the charge share line and reduces the voltage differential that must be swung to write data into the cell.
While the method and device of U.S. Pat. No. 6,934,213 can allow a reduction of the power required by the RAM, noise margin failures may occur. Moreover, about one quarter of the charge of the bitline will return to the bitline again, and the charge sharing mechanism of U.S. Pat. No. 6,934,213 allows only charge sharing within one column of the RAM.
It is an object of the present subject matter to provide a method of writing data to a memory device and a memory device which allow substantially avoiding or at least reducing the above-mentioned problems of the state of the art.